View AT91CAP9S500A09_4571332.PDF datasheet online --- IC-ON-LINE

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Features
* Incorporates the ARM926EJ-STM ARM(R) Thumb(R) Processor
- DSP Instruction Extensions, ARM Jazelle(R) Technology for Java(R) Acceleration - 16 Kbyte Data Cache, 16 Kbyte Instruction Cache, Write Buffer - 220 MIPS at 200 MHz - Memory Management Unit - EmbeddedICETM In-circuit Emulation, Debug Communication Channel Support Additional Embedded Memories - One 32 Kbyte Internal ROM, Two-cycle Access at Maximum Matrix Speed - One 32 Kbyte Internal SRAM, Single-cycle Access at Maximum Matrix Speed External Bus Interface (EBI) - EBI Supports Mobile DDR, SDRAM, Low Power SDRAM, Static Memory, Synchronous CellularRAM, ECC-enabled NAND Flash and CompactFlashTM Metal Programmable (MP) Block - 500,000 Gates/250,000 Gates Metal Programmable Logic (through 5 Metal Layers) for AT91CAP9S500A/AT91CAP9S250A Respectively - Ten 512 x 36-bit Dual Port RAMs - Eight 512 x 72-bit Single Port RAMs - High Connectivity for Up to Three AHB Masters and Four AHB Slaves - Up to Seven AIC Interrupt Inputs - Up to Four DMA Hardware Handshake Interfaces - Delay Lines for Double Data Rate Interface - UTMI+ Full Connection - Up to 77 Dedicated I/Os LCD Controller - Supports Passive or Active Displays - Up to 24 Bits per Pixel in TFT Mode, Up to 16 Bits per Pixel in STN Color Mode - Up to 16M Colors in TFT Mode, Resolution Up to 2048x2048, Supports Wider Screen Buffers Image Sensor Interface - ITU-R BT. 601/656 External Interface, Programmable Frame Capture Rate - 12-bit Data Interface for Support of High Sensibility Sensors - SAV and EAV Synchronization, Preview Path with Scaler, YCbCr Format USB 2.0 Full Speed (12 Mbits per second) OHCI Host Double Port - Dual On-chip Transceivers - Integrated FIFOs and Dedicated DMA Channels USB 2.0 High Speed (480 Mbits per second) Device Port - On-chip Transceiver, 4 Kbyte Configurable Integrated DPRAM - Integrated FIFOs and Dedicated DMA Channels - Integrated UTMI+ Physical Interface Ethernet MAC 10/100 Base T - Media Independent Interface (MII) or Reduced Media Independent Interface (RMII) - 128-byte FIFOs and Dedicated DMA Channels for Receive and Transmit Multi-Layer Bus Matrix - Twelve 32-bit-layer Matrix, Allowing a Maximum of 38.4 Gbps of On-chip Bus Bandwidth at Maximum 100 MHz System Clock Speed - Boot Mode Select Option, Remap Command Fully-featured System Controller, Including - Reset Controller, Shutdown Controller
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Customizable Microcontroller Processor AT91CAP9S500A AT91CAP9S250A Summary Preliminary
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6264CS-CAP-24-Mar-09
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- Four 32-bit Battery Backup Registers for a Total of 16 Bytes - Clock Generator and Power Management Controller - Advanced Interrupt Controller and Debug Unit - Periodic Interval Timer, Watchdog Timer and Real-Time Timer Reset Controller (RSTC) - Based on Two Power-on Reset Cells, Reset Source Identification and Reset Output Control Shutdown Controller (SHDC) - Programmable Shutdown Pin Control and Wake-up Circuitry Clock Generator (CKGR) - Selectable 32768 Hz Low-power Oscillator or Internal Low-power RC Oscillator on Battery Backup Power Supply, Providing a Permanent Slow Clock - 8 to 16 MHz On-chip Oscillator - Two PLLs up to 240 MHz - One USB 480 MHz PLL Power Management Controller (PMC) - Very Slow Clock Operating Mode, Software Programmable Power Optimization Capabilities - Four Programmable External Clock Signals Advanced Interrupt Controller (AIC) - Individually Maskable, Eight-level Priority, Vectored Interrupt Sources - Two External Interrupt Sources and One Fast Interrupt Source, Spurious Interrupt Protected Debug Unit (DBGU) - 2-wire UART and Support for Debug Communication Channel, Programmable ICE Access Prevention Periodic Interval Timer (PIT) - 20-bit Interval Timer plus 12-bit Interval Counter Watchdog Timer (WDT) - Key-protected, Programmable Only Once, Windowed 16-bit Counter Running at Slow Clock Real-Time Timer (RTT) - 32-bit Free-running Backup Counter Running at Slow Clock with 16-bit Prescaler Four 32-bit Parallel Input/Output Controllers (PIOA, PIOB, PIOC and PIOD) - 128 Programmable I/O Lines Multiplexed with up to Two Peripheral I/Os - Input Change Interrupt Capability on Each I/O Line - Individually Programmable Open-drain, Pull-up Resistor and Synchronous Output DMA Controller (DMAC) - Acts as one Bus Matrix Master - Embeds 4 Unidirectional Channels with Programmable Priority, Address Generation, Channel Buffering and Control - Supports Four External DMA Requests and Four Internal DMA Requests from the Metal Programmable Block (MPBlock) Twenty-two Peripheral DMA Controller Channels (PDC) One 2.0A and 2.0B Compliant CAN Controller - 16 Fully-programmable Message Object Mailboxes, 16-bit Time Stamp Counter Two Multimedia Card Interfaces (MCI) - SDCard/SDIO and MultiMediaTM Card 3.31 Compliant - Supports SDHC Devices - Automatic Protocol Control and Fast Automatic Data Transfers with PDC Two Synchronous Serial Controllers (SSC) - Independent Clock and Frame Sync Signals for Each Receiver and Transmitter - IS Analog Interface Support, Time Division Multiplex Support - High-speed Continuous Data Stream Capabilities with 32-bit Data Transfer One AC97 Controller (AC97C) - 6-channel Single AC97 Analog Front End Interface, Slot Assigner
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AT91CAP9S500/AT91CAP9S250A
6264CS-CAP-24-Mar-09
AT91CAP9S500/AT91CAP9S250A
* Three Universal Synchronous/Asynchronous Receiver Transmitters (USART)
- Individual Baud Rate Generator, IrDA(R) Infrared Modulation/Demodulation, Manchester Encoding/Decoding - Support for ISO7816 T0/T1 Smart Card, Hardware Handshaking, RS485 Support Two Master/Slave Serial Peripheral Interface (SPI) - 8- to 16-bit Programmable Data Length, Four External Peripheral Chip Selects - Synchronous Communications at Up to 90 Mbits/sec One Three-channel 16-bit Timer/Counters (TC) - Three External Clock Inputs, Two Multi-purpose I/O Pins per Channel - Double PWM Generation, Capture/Waveform Mode, Up/Down Capability One Four-channel 20-bit PWM Controller (PWMC) One Two-wire Interface (TWI) - Master and Slave Mode Support, All Two-wire Atmel EEPROMs Supported One 8-channel, 10-bit Analog-to-Digital Converter (ADC) - Eight Channels Multiplexed with Digital I/Os IEEE(R) 1149.1 JTAG Boundary Scan on All Digital Pins Required Power Supplies: - 1.08V to 1.32V for VDDCORE and VDDBU, VDDUPLL and VDDUTMIC - 3.0V to 3.6V for VDDOSC, VDDPLL and VDDIOP0 (Peripheral I/Os) and VDDANA (ADC) - Programmable 1.65V to 1.95V or 3.0V to 3.6V for VDDIOP1 (Peripheral I/Os), VDDIOM (Memory I/Os) and VDDMPIOA/VDDMPIOB (MP Block I/Os) Available in 400-ball LFBGA RoHS-compliant Package Can also be Delivered in a 324-ball TFBGA RoHS-compliant Package According to User Needs
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1. Description
The AT91CAP9S500A/AT91CAP9S250A family is based on the integration of an ARM926EJ-S processor with fast ROM and SRAM memories, and a wide range of peripherals. By providing up to 500K gates of metal programmable logic, AT91CAP9S500A/AT91CAP9S250A is the ideal platform for creating custom designs. The AT91CAP9S500A/AT91CAP9S250A embeds a USB High-speed Device, a 2-port USB OHCI Host, an LCD Controller, a 4-channel DMA Controller, and one Image Sensor Interface. It also integrates several standard peripherals, such as USART, SPI, TWI, Timer Counters, PWM generators, Multimedia Card interface, and one CAN Controller. The AT91CAP9S500A/AT91CAP9S250A is architectured on a 12-layer matrix, allowing a maximum internal bandwidth of twelve 32-bit buses. It also features one external memory bus (EBI) capable of interfacing with a wide range of memory devices. The AT91CAP9S500A/AT91CAP9S250A is packaged in a 400-ball LFBGA RoHS-compliant package. It can also be delivered in a 324-ball TFBGA RoHS-compliant package according to the customer's requirements.
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6264CS-CAP-24-Mar-09
TST
UTMI+ Transc.
Transc. Transc.
V B PL G HSLR C HSDP D FM S FSDP DM HD HDPA M HD A HDPB M IS B I IS _P IC IS _D K I _O IS HS -IS I I IS _VSYN _D1 I_ Y C 1 M LC CKNC LD C D0 LCDV -LC S LCDH YN DD S LCDD Y C 23 ON LCDD TCC DCEN K C ER ET XC ECXE K-E NT ERRS -E XC T ERXE -EC XE K/E RO ET X0 -E L R REF -R CK EMX0 ER XD -X EMDCETX 3 V 3 ED F1 IO 0 BM 0 S
System Controller JTAG Boundary Scan LCD Controller 10/100 Ethernet MAC USB High-Speed Device USB OHCI In-Circuit Emulator
TD TDI TMO TC S RTK C NT K R JT ST AG SE L
Note:
EBI
CompactFlash NAND Flash & ECC
Figure 2-1.
2. AT91CAP9S500A/AT91CAP9S250A Block Diagram
-D 3 CD CK
O A3 1
D0
PI
-M
O A0
PI
M
TW TW D CK CT RTS0 SC S0-CT RD K0 -R S2 T TXX0 -SCS2 D0-RDK2 -T X XD2 2 CA CA NT NRX NP X NPCS NPCS3 NPCS2 C1 SP S0 M CK O M SI PW IS O M 0PW M TC 3 L TI K0 OTI A0 TC O -T LK B0 IO 2 -T A IO 2 AC B2 AC97 AC 97CK AC97 FS 9 RX TK 7TX TF0-T TD 0- K1 T RD 0-T F1 DM R0 D A RQ R F0-RD1 0- K0 -RF1 DM -R 1 AK R1 AD Q3 0AD AD 7 TR IG AD VDVR E G DA F ND N ANA A
6264CS-CAP-24-Mar-09
M
PI
1. For information on signal multiplexing refer to Table 22-3, "EBI Pins and External Device Connections".
ARM926EJ-S Processor
ICache 16K bytes MMU Bus Interface DCache 16K bytes
O
MCI0_, MCI1_
SPI0_, SPI1_
B
0M
PI
O
B4
4
4
FIFO LUT FIFO FIFO DMA I D FIFO DMA DMA DMA DMA
MASTER
SLAVE
FIQ IRQ0-IRQ1
AIC
DBGU
DRXD DTXD PCK0-PCK3
PDC
Image Sensor Interface
PMC
PLLRCA
PLLA
PLLRCB
PLLB
XIN XOUT 12-layer Matrix
OSC
DDRSDR Controller
WDT
PIT Burst Cellular Memory Controller PIOA PIOB PIOC PIOD APB 10x DPR 512x36 PDC PDC CAN SPI0 SPI1 PWMC TC0 TC1 TC2 AC97C USART0 USART1 USART2 SSC0 SSC1 PDC PDC PDC TWI PDC 8-channel 10-bit ADC Metal Programable Block 500K Gates (CAP9500) 250K Gates (CAP9250) 8x SPR 512x72 ROM 32Kbytes Peripheral Bridge SRAM 32Kbytes 4-channel DMA
4 GPREG
D0-D15 A0/NBS0 A1/NBS2/NWR2 A2-A15, A18-A22 A16/BA0 A17/BA1 NCS0 NCS1/BCCS NRD NWR0/NWE NWR1/NBS1 NWR3/NBS3 SDCK, SDCKN SDCS DQS0, DQS1 SDCKE/BCCRE RAS/BCADV, CAS/BCOE SDWE/BCWE, SDA10 NANDOE, NANDWE BCOWAIT
XIN32 XOUT32
OSC
RTT Static Memory Controller
SHDN WKUP 24-channel Peripheral DMA
SHDC
AT91CAP9S500A/AT91CAP9S250A Block Diagram
VDDBU
POR
RSTC
VDDCORE
POR
NWAIT A23-A24 NCS2 NCS3/NANDCS NCS4/CFCS0 NCS5/CFCS1 A25/CFRNW CFCE1-CFCE2 D16-D31
AT91CAP9S500/AT91CAP9S250A
D L L
NRST
PDC
MCI0 MCI1
AT91CAP9S500/AT91CAP9S250A
3. Signal Description
Table 3-1 gives details on the signal name classified by peripheral. Table 3-1.
Signal Name
Signal Description List
Function Power Supplies Type Active Level Comments
VDDIOM VDDIOP0 VDDIOP1 VDDIOMPA VDDIOMPB VDDBU VDDPLL VDDUTMII VDDUTMIC VDDUPLL VDDANA VDDCORE GND GNDPLL GNDUTMII GNDUTMIC GNDUPLL GNDANA GNDBU GNDTHERMAL
EBI I/O Lines Power Supply Peripherals I/O Lines Power Supply Peripherals I/O Lines Power Supply MP Block I/O A Lines Power Supply MP Block I/O B Lines Power Supply Backup I/O Lines Power Supply PLL Power Supply USB UTMI+ Interface Power Supply USB UTMI+ Core Power Supply USB UTMI+ PLL Power Supply ADC Analog Power Supply Core Chip Power Supply Ground PLL Ground USB UTMI+ Interface Ground USB UTMI+ Core Ground USB UTMI+ PLL Ground ADC Analog Ground Backup Ground Thermal Ground Ball
Power Power Power Power Power Power Power Power Power Power Power Power Ground Ground Ground Ground Ground Ground Ground Ground
1.65V to 3.6V 3.0V to 3.6V 1.65V to 3.6V 1.65V to 3.6V 1.65V to 3.6V 1.08V to 1.32V 3.0V to 3.6V 3.0V to 3.6V 1.08V to 1.32V 1.08V to 1.32V 3.0V to 3.6V 1.08V to 1.32V
Thermally coupled with package substrate
Clocks, Oscillators and PLLs XIN XOUT XIN32 XOUT32 PLLRCA PLLRCB PCK0 - PCK3 Main Oscillator Input Main Oscillator Output Slow Clock Oscillator Input Slow Clock Oscillator Output PLL A Filter PLL B Filter Programmable Clock Output Input Output Input Output Input Input Output
Shutdown, Wakeup Logic SHDN WKUP Shutdown Control Wake-Up Input Output Input Do not tie over VDDBU Accept between 0V and VDDBU
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6264CS-CAP-24-Mar-09
Table 3-1.
Signal Name
Signal Description List (Continued)
Function ICE and JTAG Type Active Level Comments
NTRST TCK TDI TDO TMS JTAGSEL RTCK
Test Reset Signal Test Clock Test Data In Test Data Out Test Mode Select JTAG Selection Return Test Clock Reset/Test
Input Input Input Output Input Input Output
Low
No pull-up resistor No pull-up resistor No pull-up resistor
No pull-up resistor Pull-down resistor
NRST TST BMS
Microcontroller Reset Test Mode Select Boot Mode Select Debug Unit - DBGU
I/O Input Input
Low
Pull-up resistor Pull-down resistor Pull-up resistor
DRXD DTXD
Debug Receive Data Debug Transmit Data
Input Output
Advanced Interrupt Controller - AIC IRQ0 - IRQ1 FIQ External Interrupt Inputs Fast Interrupt Input Input Input
PIO Controller - PIOA - PIOB - PIOC - PIOD PA0 - PA31 PB0 - PB31 PC0 - PC31 PD0 - PD31 Parallel IO Controller A Parallel IO Controller B Parallel IO Controller C Parallel IO Controller D I/O I/O I/O I/O Pulled-up input at reset Pulled-up input at reset Pulled-up input at reset Pulled-up input at reset
Direct Memory Access Controller - DMA DMARQ0-DMARQ3 DMA Requests Input External Bus Interface - EBI D0 - D31 A0 - A25 NWAIT Data Bus Address Bus External Wait Signal I/O Output Input Low Pulled-up input at reset 0 at reset
Static Memory Controller - SMC NCS0 - NCS5 NWR0 - NWR3 NRD NWE NBS0 - NBS3 Chip Select Lines Write Signal Read Signal Write Enable Byte Mask Signal Output Output Output Output Output Low Low Low Low Low
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AT91CAP9S500/AT91CAP9S250A
6264CS-CAP-24-Mar-09
AT91CAP9S500/AT91CAP9S250A
Table 3-1.
Signal Name
Signal Description List (Continued)
Function CompactFlash Support Type Active Level Comments
CFCE1 - CFCE2 CFOE CFWE CFIOR CFIOW CFRNW CFCS0 - CFCS1
CompactFlash Chip Enable CompactFlash Output Enable CompactFlash Write Enable CompactFlash IO Read CompactFlash IO Write CompactFlash Read Not Write CompactFlash Chip Select Lines NAND Flash Support
Output Output Output Output Output Output Output
Low Low Low Low Low
Low
NANDCS NANDOE NANDWE
NAND Flash Chip Select NAND Flash Output Enable NAND Flash Write Enable DDR/SDRAM Controller
Output Output Output
Low Low Low
SDCK SDCKN DQS0 - DQS1 DQM0 - DQM1 DQM2 - DQM3 SDCKE SDCS BA0 - BA1 SDWE RAS - CAS SDA10
DDR/SDRAM Clock DDR Inverted Clock DDR Data Qualifier Strobes DDR/SDRAM Data Masks DDR/SDRAM Data Masks DDR/SDRAM Clock Enable DDR/SDRAM Controller Chip Select DDR/SDRAM Bank Select DDR/SDRAM Write Enable DDR/SDRAMRow and Column Signal DDR/SDRAM Address 10 Line
Output Output I/O Output Output Output Output Output Output Output Output Low Low High Low
Burst CellularRAM Controller BCCK BCCRE BCADV BCWE BCOE BCOWAIT Burst CellularRAM Clock Burst CellularRAM Enable Burst CellularRAM Burst Advance Signal Burst CellularRAM Write Enable Burst CellularRAM Output Enable Burst CellularRAM Output Wait Output Output Output Output Output Input
Multimedia Card Interface MCI MCIx_CK MCIx_CD MCIx_D0 - D3 Multimedia Card Clock Multimedia Card Command Multimedia Card Data Output I/O I/O
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6264CS-CAP-24-Mar-09
Table 3-1.
Signal Name
Signal Description List (Continued)
Function Type Active Level Comments
Universal Synchronous Asynchronous Receiver Transmitter USART SCKx TXDx RXDx RTSx CTSx USARTx Serial Clock USARTx Transmit Data USARTx Receive Data USARTx Request To Send USARTx Clear To Send I/O I/O Input Output Input
Synchronous Serial Controller - SSC TDx RDx TKx RKx TFx RFx SSCx Transmit Data SSCx Receive Data SSCx Transmit Clock SSCx Receive Clock SSCx Transmit Frame Sync SSCx Receive Frame Sync AC97 Controller - AC97C AC97RX AC97TX AC97FS AC97CK AC97 Receive Signal AC97 Transmit Signal AC97 Frame Synchronization Signal AC97 Clock signal Timer/Counter - TC TCLKx TIOAx TIOBx TC Channel x External Clock Input TC Channel x I/O Line A TC Channel x I/O Line B Input I/O I/O Input Output Output Input Output Input I/O I/O I/O I/O
Pulse Width Modulation Controller- PWMC PMWx Pulse Width Modulation Output Output
Serial Peripheral Interface - SPI SPIx_MISO SPIx_MOSI SPIx_SPCK SPIx_NPCS0 SPIx_NPCS1 - SPIx_NPCS3 Master In Slave Out Master Out Slave In SPI Serial Clock SPI Peripheral Chip Select 0 SPI Peripheral Chip Select Two-Wire Interface - TWI TWD TWCK Two-wire Serial Data Two-wire Serial Clock I/O I/O I/O I/O I/O I/O Output Low Low
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AT91CAP9S500/AT91CAP9S250A
6264CS-CAP-24-Mar-09
AT91CAP9S500/AT91CAP9S250A
Table 3-1.
Signal Name
Signal Description List (Continued)
Function CAN Controller Type Active Level Comments
CANRX CANTX
CAN input CAN output LCD Controller - LCDC
Input Output
LCDD0 - LCDD23 LCDVSYNC LCDHSYNC LCDDOTCK LCDDEN LCDCC
LCD Data Bus LCD Vertical Synchronization LCD Horizontal Synchronization LCD Dot Clock LCD Data Enable LCD Contrast Control Ethernet 10/100 EMAC
Input Output Output Output Output Output
ETXCK/EREFCK ERXCK ETXEN ETX0-ETX3 ETXER ERXDV ERX0-ERX3 ERXER ECRS ECOL EMDC EMDIO EF100
Transmit Clock or Reference Clock Receive Clock Transmit Enable Transmit Data Transmit Coding Error Receive Data Valid Receive Data Receive Error Carrier Sense and Data Valid Collision Detect Management Data Clock Management Data Input/Output Force 100Mbit/sec. USB High Speed Device
Input Input Output Output Output Input Input Input Input Input Output I/O Output High
MII only, REFCK in RMII MII only
ETX0-ETX1 only in RMII MII only RXDV in MII, CRSDV in RMII ERX0-ERX1 only in RMII
MII only MII only
RMII only
FSDM FSDP HSDM HSDP VBG PLLRCU
USB Full Speed Data USB Full Speed Data + USB High Speed Data USB High Speed Data + Bias Voltage Reference USB PLL Test Pad
Analog Analog Analog Analog Analog Analog
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6264CS-CAP-24-Mar-09
Table 3-1.
Signal Name
Signal Description List (Continued)
Function OHCI USB Host Port Type Active Level Comments
HDPA HDMA HDPB HDMB
USB Host Port A Data + USB Host Port A Data USB Host Port B Data + USB Host Port B Data ADC
Analog Analog Analog Analog
AD0-AD7 ADVREF ADTRIG
Analog Inputs ADC Voltage Reference ADC Trigger
Analog Analog Input Image Sensor Interface - ISI
ISI_D0-ISI_D11 ISI_MCK ISI_HSYNC ISI_VSYNC ISI_PCK
Image Sensor Data Image Sensor Reference Clock Image Sensor Horizontal Synchro Image Sensor Vertical Synchro Image Sensor Data Clock MPBLOCK - MPB
Input Output Input Input Input
MPIOA0-MPIOA31 MPIOB0-MPIOB44
MPBlock I/Os A MPBlock I/Os B
I/O I/O
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AT91CAP9S500/AT91CAP9S250A
6264CS-CAP-24-Mar-09
AT91CAP9S500/AT91CAP9S250A
4. Package and Pinout
The AT91CAP9S500A/AT91CAP9S250A is available in two packages: * a 400-ball RoHS-compliant LFBGA package, 17 x 17 mm, 0.8 mm ball pitch * a 324-ball RoHS-compliant TFBGA package, 15 x 15 mm, 0.8 mm ball pitch
4.1
400-ball LFBGA Package Outline
Figure 4-1 shows the orientation of the 400-ball BGA Package. A detailed mechanical description is given in the section "AT91CAP9S500A/AT91CAP9S250A Mechanical Characteristics" of the product datasheet. Figure 4-1. 400-ball LFBGA Package Outline and Marking (Top View)
Top View
20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
CAP9
ABCDEF GHJ KL MNPRT UV W A1 Corner
Y
A1 Corner
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6264CS-CAP-24-Mar-09
4.2
400-ball LFBGA Package Pinout
AT91CAP9S500A/AT91CAP9S250A Pinout for 400-ball BGA Package
Pin F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 G17 Signal Name PA3 PA4 PA8 PA5 PA6 VDDIOM VDDIOP0 PC24 NC VDDCORE GNDIO PB23 PB6 NC NC NC GNDPLL WKUP0 SHDW PLLRCA PA7 PA10 PA11 PA9 PA12 PD10 GNDIO GNDCORE VDDIOP0 PC8 PB25 PB21 PB8 PB0 PB2 NC VDDPLL Pin L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 L17 L18 L19 L20 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 M15 M16 M17 Signal Name PA22 PA25 PA29 PA31 PD6 GNDIO GNDCORE PA18 GNDTHERMAL GNDTHERMAL GNDTHERMAL GNDTHERMAL GNDCORE GNDIO VDDCORE MPIOB28 MPIOB32 MPIOB34 MPIOB31 MPIOB29 PA26 PA30 PD11 PD12 PD13 PD15 GNDCORE PA28 GNDTHERMAL GNDTHERMAL GNDTHERMAL GNDTHERMAL NRD MPIOB26 GNDIO MPIOB16 GNDCORE Pin T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 U1 U2 U3 U4 U5 U6 U7 U8 U9 U10 U11 U12 U13 U14 U15 U16 U17 Signal Name PD22 PD23 PD30 VDDCORE SDCS DQS0 D4 D11 D14 SDA10 VDDCORE MPIOA0 MPIOA9 GNDIO MPIOA25 MPIOA24 MPIOA29 MPIOB3 MPIOB17 MPIOB18 PD25 PD31 BCCLK A0 D0 D1 NWR1 DQS1 A7 A13 A20 GNDIO MPIOA4 MPIOA11 MPIOA16 VDDMPIOA MPIOA23
Table 4-1.
Pin A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 PC5 PC3 PC2 PC1 PC0 BMS NRST
Signal Name
GNDCORE PB18 PB17 PB14 PB15 GNDANA PB26 VDDIOP0 GNDIO FSDP FSDM HSDP HSDM PC17 PC16 PC14 PC11 PC10 PC9 TDO TCK PB20 PB19 PB13 ADVREF PB16 PB27 PB24 HDMA VDDIOP0
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AT91CAP9S500/AT91CAP9S250A
6264CS-CAP-24-Mar-09
AT91CAP9S500/AT91CAP9S250A
Table 4-1.
Pin B18 B19 B20 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 GNDIO VDDUTMII GNDUTMII PC23 PC22 PC21 PC20 PC18 PC15 PC12 PC6 NTRST TDI VDDANA PB12 PB29 PB9 PB7 HDPA HDPB VDDUPLL VDDUTMIC VBG PC29 PC28 PC27 PC26 PC25 PC19 NANDOE PC7 GNDIO TMS NC PB31 PB22 VDDCORE PB3
AT91CAP9S500A/AT91CAP9S250A Pinout for 400-ball BGA Package (Continued)
Pin G18 G19 G20 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 H17 H18 H19 H20 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 Signal Name GNDCORE TST PLLRCB PA13 PA14 PD0 PA15 PD1 VDDIOP1 VDDCORE GNDIO GNDIO PB10 PB4 VDDMPIOB JTAGSEL GNDCORE GNDPLL NC VDDCORE MPIOB44 XOUT32 XIN32 PD3 PD2 PD5 PA17 PA19 VDDIOP0 PA16 GNDCORE GNDTHERMAL GNDTHERMAL GNDTHERMAL GNDTHERMAL GNDIO GNDBU GNDBU Pin M18 M19 M20 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 N16 N17 N18 N19 N20 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 Signal Name MPIOB27 MPIOB25 MPIOB24 PD7 PD8 PD16 PD19 PD20 PD29 GNDIO VDDIOM NCS1 VDDCORE A3 A6 VDDCORE MPIOB11 MPIOB13 MPIOB12 MPIOB14 MPIOB15 MPIOB22 MPIOB23 PD9 PD14 PD18 PD27 PD28 VDDIOM NWR3 D8 D10 GNDIO A9 A12 NC MPIOB8 MPIOB0 Pin U18 U19 U20 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 V20 W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 W15 Signal Name MPIOA28 MPIOB6 MPIOB9 PD26 RAS SDCKE D3 VDDIOM D5 D9 D15 A11 GNDCORE A22 MPIOA1 MPIOA6 MPIOA10 MPIOA13 MPIOA17 MPIOA20 MPIOA27 MPIOB5 VDDMPIOB SDWE BCOWAIT NANDWE GNDIO D6 A2 A5 A14 A17 A19 NWR0 MPIOA2 MPIOA5 MPIOA8 MPIOA12
Signal Name
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6264CS-CAP-24-Mar-09
Table 4-1.
Pin D16 D17 D18 D19 D20 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 PB1 HDMB
AT91CAP9S500A/AT91CAP9S250A Pinout for 400-ball BGA Package (Continued)
Pin J16 J17 J18 J19 J20 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 K15 K16 K17 K18 K19 K20 Signal Name MPIOB42 MPIOB39 MPIOB43 MPIOB41 GNDIO PD4 PA21 PA24 PA27 PA23 GNDIO PA20 VDDCORE GNDTHERMAL GNDTHERMAL GNDTHERMAL GNDTHERMAL GNDCORE MPIOB33 MPIOB30 MPIOB35 MPIOB38 MPIOB40 MPIOB37 MPIOB36 Pin P16 P17 P18 P19 P20 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 Signal Name MPIOB1 MPIOB7 MPIOB10 MPIOB21 VDDMPIOB PD21 PD17 PD24 CAS VDDCORE D2 D7 VDDIOM D13 D12 VDDIOM A16 VDDIOM NC NC NC MPIOB2 MPIOB4 MPIOB19 MPIOB20 Pin W16 W17 W18 W19 W20 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20 Signal Name MPIOA15 MPIOA21 MPIOA22 GNDIO VDDCORE SDCK SDCKN A1 GNDCORE A4 A8 A10 A15 A18 A21 NCS0 MPIOA3 MPIOA7 VDDMPIOA MPIOA14 MPIOA18 MPIOA19 MPIOA26 MPIOA30 MPIOA31
Signal Name
PLLRCU GNDUTMIC GNDUPLL PC30 PA2 PA1 PA0 PC31 GNDIO VDDCORE PC13 PC4 RTCK VDDIOP0 PB30 PB28 PB11 PB5 NC VDDPLL VDDBU XIN XOUT
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AT91CAP9S500/AT91CAP9S250A
4.3 324-ball TFBGA Package Outline
Figure 4-2 shows the orientation of the 324-ball TFBGA green package. A detailed mechanical description is given in the section "AT91CAP9S500A/AT91CAP9S250A Mechanical Characteristics" of the product datasheet. Figure 4-2. 324-ball TFBGA Package Outline and Marking (Top View)
Top View
18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 ABCDEFGHJ KLMNPRTUV A1 Corner A1 Corner
CAP9
4.4
324-ball TFBGA Package Pinout
The pin assignment for the 324-ball TFBGA package is customizable and dependent upon the needs of the user. Important: It is possible to partially or totally remove the connections to dedicated Metal Programmable I/0s: MPIOAO-MPIOA31 and MPIOB0-MPIOB44. Likewise, PA16-PA31, PB21PB31, PDC0-PC27, PD0-PD10 can be partially or totally disconnected. However, it is incumbent upon the user to ensure that the associated functionality removed is not needed for the intended application. Refer to Section 10.3.1 on page 42, Section 10.3.2 on page 43, Section 10.3.3 on page 44, Section 10.3.4 on page 45 for information on PIO multiplexing and to verify functionality before disconnecting signals.
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6264CS-CAP-24-Mar-09
5. Power Considerations
5.1 Power Supplies
The AT91CAP9S500A/AT91CAP9S250A has several types of power supply pins: * VDDCORE pins: Power the core, including the processor, the embedded memories and the peripherals; voltage range between1.08V and 1.32V, 1.2V nominal. * VDDIOM pins: Power the External Bus Interface; voltage ranges between 1.65V and 1.95V (1.8V nominal) or between 3.0V and 3.6V (3.3V nominal). * VDDIOP0 pins: Power the Peripherals I/O lines and the USB transceivers; voltage range between 3.0V and 3.6V, 3.3V nominal. * VDDIOP1 pins: Power the Peripherals I/O lines involving the Image Sensor Interface; voltage ranges from 1.65V to 3.6V, 1.8V, 2.5V, 3V or 3.3V nominal. * VDDIOMPA pins: Power the MP Block I/O A lines; voltage ranges from 1.65V to 3.6V, 1.8V, 2.5V, 3V or 3.3V nominal. * VDDIOMPB pins: Power the dedicated MP Block I/O B lines; voltage ranges from 1.65V to 3.6V, 1.8V, 2.5V, 3V or 3.3V nominal. * VDDBU pin: Powers the Slow Clock oscillator and a part of the System Controller; voltage range between1.08V and 1.32V, 1.2V nominal. * VDDPLL pin: Powers the PLL cells; voltage ranges between 3.0V to 3.6V, 3.3V nominal. * VDDUTMII pin: Powers the UTMI+ interface; voltage ranges from 3.0V to 3.6V, 3.3V nominal. * VDDUTMIC pin: Powers the UTMI+ core; voltage ranges between 1.08V and 1.32V, 1.2V nominal. * VDDUPLL pin: Powers the USB PLL cell; voltage ranges between 1.08V and 1.32V, 1.2V nominal. * VDDANA pin: Powers the ADC cell; voltage ranges between 3.0V and 3.6V, 3.3V nominal. The power supplies VDDIOM, VDDIOP0 and VDDIOP1 are identified in the pinout table and the multiplexing tables. These supplies enable the user to power the device differently for interfacing with memories and for interfacing with peripherals. Ground pins GNDIO are common to VDDIOM, VDDIOP0, VDDIOP1, VDDIOMPA and VDDIOMPB pin power supplies. Separated ground pins are provided for VDDCORE, VDDBU, VDDPLL, VDDUTMII, VDDUTMIC, VDDUPLL and VDDANA. These ground pins are, respectively, GNDBU, GNDOSC, GNDPLL, GNDUTMII, GNDUTMIC, GNDUPLL and GNDANA. Special GNDTHERMAL ground balls are thermally coupled with package substrate.
5.2
Power Consumption
The AT91CAP9S500A/AT91CAP9S250A consumes about 190 A of static current on VDDCORE at 25C. On VDDBU, the current does not exceed 4 A @25C. For dynamic power consumption and more details, refer to the Power Consumption section and tables in the Electrical Characteristics section of the product datasheet.
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AT91CAP9S500/AT91CAP9S250A
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AT91CAP9S500/AT91CAP9S250A
5.3 Programmable I/O Lines Power Supplies
The power supply pins VDDIOM, VDDMPIOA and VDDMPIOB accept two voltage ranges. This allows the device to reach its maximum speed either out of 1.8V or 3.3V external memories. The target maximum speed is 100 MHz on the pin DDR/SDR and MPIOA or MPIOB pins loaded with 30 pF for power supply at 1.8V and 50 pF for power supply at 3.3V. The other signals (control, address and data signals) do not go over 50 MHz. The voltage ranges are determined by programming registers in the Chip Configuration registers located in the Matrix User Interface. At reset, the selected voltage defaults to 3.3V nominal and power supply pins can accept either 1.8V or 3.3V. Obviously, the device cannot reach its maximum speed if the voltage supplied to the pins is 1.8V only. The user must make sure to program the EBI voltage range before getting the device out of its Slow Clock Mode.
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6264CS-CAP-24-Mar-09
6. I/O Line Considerations
6.1 JTAG Port Pins
TMS, TDI and TCK are Schmitt trigger inputs and have no pull-up resistors. TDO and RTCK are outputs, driven at up to VDDIOP0, and have no pull-up resistors. The JTAGSEL pin is used to select the JTAG boundary scan when asserted at a high level. It integrates a permanent pull-down resistor of about 15 k to GNDBU so that it can be left unconnected for normal operations. The NTRST signal is described in Section 6.3 "Reset Pins" on page 18. All the JTAG signals are supplied with VDDIOP0.
6.2
Test Pin
The TST pin is used for manufacturing test purposes when asserted high. It integrates a permanent pull-down resistor of about 15 k to GNDBU so that it can be left unconnected for normal operations. Driving this line at a high level leads to unpredictable results. This pin is supplied with VDDBU.
6.3
Reset Pins
NRST is an open-drain output integrating a non-programmable pull-up resistor. It can be driven with voltage at up to VDDIOP0. NTRST is an input which allows reset of the JTAG Test Access port. It has no action on the processor. As the product integrates power-on reset cells that manage the processor and the JTAG reset, the NRST pin can be left unconnected. The NRST pin integrates a permanent pull-up resistor of 90 k minimum to VDDIOP0. The NRST signal is inserted in the Boundary Scan.
6.4
PIO Controllers
All the I/O lines which are managed by the PIO Controllers integrate a programmable pull-up resistor of 90 k minimum. Programming of this pull-up resistor is performed independently for each I/O line through the PIO Controllers. After reset, all the I/O lines default as inputs with pull-up resistors enabled, except those multiplexed with the External Bus Interface signals that must be enabled as Peripheral at reset. This is indicated in the column "Reset State" of the PIO Controller multiplexing tables.
6.5
Shutdown Logic Pins
The SHDN pin is an output only, which is driven by the Shutdown Controller only at low level. It can be tied high with an external pull-up resistor at VDDBU only. The pin WKUP is an input-only. It can accept voltages only between 0V and VDDBU.
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AT91CAP9S500/AT91CAP9S250A
7. Processor and Architecture
7.1 ARM926EJ-S Processor
* RISC Processor based on ARM v5TEJ Architecture with Jazelle technology for Java acceleration * Two Instruction Sets - ARM High-performance 32-bit Instruction Set - Thumb High Code Density 16-bit Instruction Set * DSP Instruction Extensions * 5-Stage Pipeline Architecture: - Instruction Fetch (F) - Instruction Decode (D) - Execute (E) - Data Memory (M) - Register Write (W) * 16-Kbyte Data Cache, 16-Kbyte Instruction Cache - Virtually-addressed 4-way Associative Cache - Eight words per line - Write-through and Write-back Operation - Pseudo-random or Round-robin Replacement * Write Buffer - Main Write Buffer with 16-word Data Buffer and 4-address Buffer - DCache Write-back Buffer with 8-word Entries and a Single Address Entry - Software Control Drain * Standard ARM v4 and v5 Memory Management Unit (MMU) - Access Permission for Sections - Access Permission for large pages and small pages can be specified separately for each quarter of the page - 16 embedded domains * Bus Interface Unit (BIU) - Arbitrates and Schedules AHB Requests - Separate Masters for both instruction and data access providing complete Matrix system flexibility - Separate Address and Data Buses for both the 32-bit instruction interface and the 32-bit data interface - On Address and Data Buses, data can be 8-bit (Bytes), 16-bit (Half-words) or 32-bit (Words)
7.2
Bus Matrix
* 12-layer Matrix, handling requests from 12 masters * Programmable Arbitration strategy - Fixed-priority Arbitration 19
6264CS-CAP-24-Mar-09
- Round-Robin Arbitration, either with no default master, last accessed default master or fixed default master * Burst Management - Breaking with Slot Cycle Limit Support - Undefined Burst Length Support * One Address Decoder provided per Master - Three different slaves may be assigned to each decoded memory area: one for internal boot, one for external boot, one after remap * Boot Mode Select - Non-volatile Boot Memory can be internal or external - Selection is made by BMS pin sampled at reset * Remap Command - Allows Remapping of an Internal SRAM in Place of the Boot Non-Volatile Memory - Allows Handling of Dynamic Exception Vectors
7.3
Matrix Masters
The Bus Matrix of the AT91CAP9S500A/AT91CAP9S250A manages twelve Masters and thus each master can perform an access concurrently with the others, assuming that the slave it accesses is available. Each Master has its own decoder, which is defined specifically for each master. In order to simplify the addressing, all the masters have the same decoding. Table 7-1.
Master 0 Master 1 Master 2 Master 3 Master 4 Master 5 Master 6 Master 7 Master 8 Master 9 Master 10 Master 11
List of Bus Matrix Masters
ARM926TM Instruction ARM926 Data Peripheral DMA Controller LCD Controller USB High Speed Device Controller Image Sensor Interface DMA Controller Ethernet MAC OHCI USB Host Controller MP Block Master 0 MP Block Master 1 MP Block Master 2
7.4
Matrix Slaves
The Bus Matrix of the AT91CAP9S500A/AT91CAP9S250A manages ten Slaves. Each Slave has its own arbiter, thus permitting a different arbitration per Slave to be programmed.
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AT91CAP9S500/AT91CAP9S250A
The LCD Controller, the USB Host and the USB High Speed Device have a user interface mapped as a Slave of the Matrix. They share the same layer, as programming them does not require a high bandwidth. Table 7-2.
Slave 0 Slave 1
List of Bus Matrix Slaves
Internal SRAM 32 Kbytes MP Block Slave 0 (MP Block Internal Memories) Internal ROM LCD Controller User Interface
Slave 2 USB High Speed Device Interface OHCI USB Host Interface Slave 3 Slave 4 Slave 5 Slave 6 Slave 7 Slave 8 Slave 9 MP Block Slave 1 (MP Block Internal Memories) External Bus Interface DDR Controller Port 2 DDR Controller Port 3 MP Block Slave 2 (MP Block External Chip Selects) MP Block Slave 3 (MP Block Internal Peripherals) Internal Peripherals for AT91CAP9
7.5
Master-to-Slave Access
All the Masters can normally access all the Slaves. However, some paths do not make sense, such as allowing access from the Ethernet MAC to the Internal Peripherals. Thus, these paths are forbidden or simply not wired, and shown as "-" in Table 7-3, "AT91CAP9S500A/AT91CAP9S250A Masters to Slaves Access," on page 22.
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6264CS-CAP-24-Mar-09
Table 7-3.
Master
AT91CAP9S500A/AT91CAP9S250A Masters to Slaves Access
0 ARM926 Instruction 1 2 Peripheral DMA Ctrl 3 4 5 Image Sensor Interface 6 7 8 OHCI USB Host Ctrl 9 MP Block Master 0 10 MP Block Master 1 11 MP Block Master 2 X X X X X X X X X(1) X(1) X X X
USB High Speed Device Ctrl
ARM926 Data
Slave
0 1
Internal SRAM 32 Kbytes MP Block Slave 0 Internal ROM LCD Controller User Interface
X X X X
X X X X
X X X -
X X X -
X X X -
X X X -
X X X -
X X X -
Ethernet MAC
DMA Ctrl
LCDCtrl
X X X -
X X X X
X X X X
2
USB High Speed Device Interface OHCI USB Host Interface
X
X
-
-
-
-
X
-
-
X
X
X X X
X X X
X X
X X
X X
X X
X X
X X
X X
X X X
X X X
3 4 5 6
MPBlock Slave 1 External Bus Interface
DDR Port 0 DDR Port 1 DDR Port 2 DDR Port 3
X -
X
X
(1)
X
(1)
X
(1)
X
(1)
X
(1)
X
(1)
X
(1)
X
(1)
X
(1)
X(1) X X X X X X X X X
X(1) X X -
X(1) X X -
X(1) X X -
X(1) X X X
X(1) X X -
X(1) X X -
X(1) X X X
X(1) X X X
7 8 9
MPBlock Slave 2 MPBlock Slave 3 Internal Peripherals
Note:
1. DDR Port 2 or Port 3 is selectable for each master through the Matrix Remap Control Register.
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AT91CAP9S500/AT91CAP9S250A
7.6 Peripheral DMA Controller
* Acting as one Matrix Master * Allows data transfers from/to peripheral to/from any memory space without any intervention of the processor. * Next Pointer Support, forbids strong real-time constraints on buffer management. * Twenty-two Channels - Two for each USART - Two for the Debug Unit - One for the TWI - One for the ADC Controller - Two for the AC97 Controller - Two for each Serial Synchronous Controller - Two for each Serial Peripheral Interface - One for the each Multimedia Card Interface The Peripheral DMA Controller handles transfer requests from the channel according to the following priorities (Low to High priorities): - DBGU Transmit Channel - USART2 Transmit Channel - USART1 Transmit Channel - USART0 Transmit Channel - AC97 Transmit Channel - SPI1 Transmit Channel - SPI0 Transmit Channel - SSC1 Transmit Channel - SSC0 Transmit Channel - DBGU Receive Channel - TWI Transmit/Receive Channel - ADC Receive Channel - USART2 Receive Channel - USART1 Receive Channel - USART0 Receive Channel - AC97 Receive Channel - SPI1 Receive Channel - SPI0 Receive Channel - SSC1 Receive Channel - SSC0 Receive Channel - MCI1 Transmit/Receive Channel - MCI0 Transmit/Receive Channel
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6264CS-CAP-24-Mar-09
7.7
DMA Controller
* Acting as one Matrix Master * Embeds 4 unidirectional channels with programmable priority * Address Generation - Source / destination address programming - Address increment, decrement or no change - DMA chaining support for multiple non-contiguous data blocks through use of linked lists - Scatter support for placing fields into a system memory area from a contiguous transfer. Writing a stream of data into non-contiguous fields in system memory - Gather support for extracting fields from a system memory area into a contiguous transfer - User enabled auto-reloading of source, destination and control registers from initially programmed values at the end of a block transfer - Auto-loading of source, destination and control registers from system memory at end of block transfer in block chaining mode - Unaligned system address to data transfer width supported in hardware * Channel Buffering - 8-word FIFO - Automatic packing/unpacking of data to fit FIFO width * Channel Control - Programmable multiple transaction size for each channel - Support for cleanly disabling a channel without data loss - Suspend DMA operation - Programmable DMA lock transfer support * Transfer Initiation - Support four External DMA Requests and four Internal DMA request from the MP Block - Support for Software handshaking interface. Memory mapped registers can be used to control the flow of a DMA transfer in place of a hardware handshaking interface * Interrupt - Programmable Interrupt generation on DMA Transfer completion Block Transfer completion, Single/Multiple transaction completion or Error condition
7.8
Debug and Test Features
* ARM926 Real-time In-circuit Emulator - Two real-time Watchpoint Units - Two Independent Registers: Debug Control Register and Debug Status Register - Test Access Port Accessible through JTAG Protocol - Debug Communications Channel * Debug Unit - Two-pin UART
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AT91CAP9S500/AT91CAP9S250A
- Debug Communication Channel Interrupt Handling - Chip ID Register * IEEE1149.1 JTAG Boundary-scan on All Digital Pins
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6264CS-CAP-24-Mar-09
8. Memories
Figure 8-1. AT91CAP9S500A/AT91CAP9S250A Memory Mapping
Address Memory Space 0x0000 0000 Internal Memories
0x0FFF FFFF
Internal Memory Mapping
0x0000 0000 0x0010 0000 0x0020 0000 Boot Memory (1) SRAM MPB SLAVE0 MPB SLAVE0 ROM LCDC
Notes : (1) Can be ROM, EBI_NCS0 or SRAM depending on BMS and RCB0, RCB1
256M Bytes
0x1000 0000 EBI Chip Select 0
0x1FFF FFFF 0x0030 0000
256M Bytes
0x0040 0000 0x0050 0000
0x2000 0000 EBI Chip Select 1/ EBI BCRAMC 256M Bytes
0x0060 0000 0x0070 0000
UDPHS USB HOST
0x2FFF FFFF
0x3000 0000 EBI Chip Select 2
0x3FFF FFFF
256M Bytes
0x0080 0000 MPB SLAVE1 0x0090 0000 MPB SLAVE1 0x00A0 0000
0x4000 0000
EBI Chip Select 3/ NAND Flash EBI Chip Select 4/ Compact Flash Slot 0 EBI Chip Select 5/ Compact Flash Slot 1 EBI DDRSDRC
256M Bytes
0x00B0 0000
MPB SLAVE1 MPB SLAVE1
0x4FFF FFFF
0x5000 0000
256M Bytes
0xFF00 0000
Peripheral Mapping
Reserved 0xFFF7 8000 UDPHS 0xFFF7 C000 TCO, TC1, TC2 0xFFF8 0000 MCI0 16K Bytes 16K Bytes 16K Bytes 16K Bytes 16K Bytes 16K Bytes 16K Bytes 0xFFFF EC00 SSC1 0xFFFA 0000 AC97C 16K Bytes 16K Bytes 16K Bytes 16K Bytes 16K Bytes 16K Bytes 16K Bytes 0xFFFF FC00 EMAC 0xFFFC 0000 ADCC 0xFFFC 4000 ISI 16K Bytes 16K Bytes 16K Bytes 16K Bytes 0xFFFF FFFF 16K Bytes 16K Bytes 0xFFFF FD00 0xFFFF FD10 0xFFFF FD20 0xFFFF FD30 0xFFFF FD40 0xFFFF FD50 0xFFFF FD60 0xFFFF FD70 SYSC 0xFFFF FFFF PMC RSTC SHDC RTT PIT WDT SCKCR GPBR Reserved 256 Bytes 16 Bytes 16 Bytes 16 Bytes 16 Bytes 16 Bytes 16 Bytes 16 Bytes 16K Bytes 0xFFFF EE00 DBGU 0xFFFF F000 AIC SPI0 0xFFFA 8000 SPI1 0xFFFA C000 CAN0 0xFFFB 0000 Reserved 0xFFFB 4000 Reserved 0xFFFF F800 0xFFFF FA00 0xFFFF F600 PIOC PIOD Reserved 512 bytes 512 bytes 512 bytes 0xFFFF F200 0xFFFF F400 PIOB 512 Bytes PIOA 512 bytes 512 bytes 512 Bytes 0xFFFF E200 0xFFFF E400 0xFFFF E600 0xFFFF E800 0xFFFF EA00 0xFFFF EB10 SSC0 16K Bytes Reserved 16K Bytes 16K Bytes
0x5FFF FFFF
0x6000 0000
System Controller Mapping
0xFFFF C000
256M Bytes
0x6FFF FFFF
0x7000 0000
256M Bytes
0xFFF8 4000 MCI1 0xFFF8 8000 TWI ECC BCRAMC DDRSDRC SMC MATRIX 512 Bytes CCFG DMA 512 Bytes 512 Bytes 512 Bytes 512 bytes 512 Bytes
0x7FFF FFFF
0x8000 0000 MPB SLAVE2 Chip Select 0
0x8FFF FFFF
256M Bytes
0xFFF8 C000 USART0 0xFFF9 0000 USART1
0x9000 0000 MPB SLAVE 2 Chip Select 1
0x9FFF FFFF
256M Bytes
0xFFF9 4000 USART2 0xFFF9 8000
0xA000 0000 MPB SLAVE 2 Chip Select 2
0xAFFF FFFF
256M Bytes
0xFFF9 C000
0xB000 0000 MPB SLAVE 2 Chip Select 3
0xBFFF FFFF
256M Bytes
0xFFFA 4000
0xC000 0000
Undefined (Abort)
768M Bytes
0xFFFB 8000 PWMC 0xFFFB C000
0xEFFF FFFF
Undefined (Abort) 0xFCFF FFFF 0xFD00 0000 MPB SLAVE3 0xFE00 0000 MPB SLAVE3 0xFF00 0000 Internal Peripherals
0xFFFF FFFF
0xF000 0000
0xFFFC 8000
208M Bytes 16M Bytes 16M Bytes 16M Bytes
Reserved 0xFFFC C000 Reserved 0xFFFF C000
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6264CS-CAP-24-Mar-09
AT91CAP9S500/AT91CAP9S250A
A first level of address decoding is performed by the Bus Matrix, i.e., the implementation of the Advanced High-performance Bus (AHB) for its Master and Slave interfaces with additional features. Decoding breaks up the 4G bytes of address space into 16 banks of 256M bytes. The banks 1 to 7 are directed to the EBI that associates these banks to the external chip selects NCS0 to NCS5 and SDCS. The bank 0 is reserved for the addressing of the internal memories, and a second level of decoding provides 1M byte of internal memory area. The banks 8 to 11 are directed to MP Block (Slave 2) and may be used to address external memories. The bank 15 is split into three parts, one reserved for the peripherals that provides access to the Advanced Peripheral Bus (APB), the two others are directed to MP Block (Slave 3) and may provide access to the MP Block APB or to other AHB peripherals. Other areas are unused and performing an access within them provides an abort to the master requesting such an access. Each Master has its own bus and its own decoder, thus allowing a different memory mapping per Master. However, in order to simplify the mappings, all the masters have a similar address decoding. Regarding Master 0 and Master 1 (ARM926 Instruction and Data), three different Slaves are assigned to the memory space decoded at address 0x0: one for internal boot, one for external boot and one after remap. Refer to Table 8-1, "Internal Memory Mapping," on page 28 for details.
8.1
Embedded Memories
* 32 Kbyte ROM - Two Cycle Access at full matrix speed * 32 Kbyte Fast SRAM - Single Cycle Access at full matrix speed * 20 Kbyte MP Block Fast Dual Port RAM (ten 512x36 DPR instances) - Used as Dual Port RAM completely managed by MP Block * 32 Kbyte MP Block Fast Single Port RAM (eight 512x72 SPR instances) - Used as Single Port RAM completely managed by MP Block
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6264CS-CAP-24-Mar-09
8.1.1
Internal Memory Mapping Table 8-1 summarizes the Internal Memory Mapping, depending on the Remap Command Bit (RBC) status and the BMS state at reset. REMAP allows the user to layout the internal SRAM bank to 0x0 to ease development. This is done by software once the system boots. Refer to the Bus Matrix Section for more details. When REMAP = 0, BMS allows the user to lay out to 0x0, at his convenience, the ROM or an external memory. This is done by way of hardware at reset.
Table 8-1.
Address
Internal Memory Mapping
ARM926 I RCB0 = 0 RCB0 = 1 BMS = 0 SRAM NCS0 ARM926 D RCB1 = 0 BMS = 1 ROM SRAM Abort RCB1 = 1 Other Masters
0x0000 0000
BMS = 0 NCS0
BMS = 1 ROM
8.1.1.1
Internal 32 Kbyte Fast SRAM The AT91CAP9S500A/AT91CAP9S250A integrates a 32 Kbyte SRAM, mapped at address 0x0010 0000, which is accessible from the AHB bus. This SRAM is single cycle accessible at full matrix speed. Internal ROM The AT91CAP9S500A/AT91CAP9S250A embeds an Internal ROM, which contains the SAM-BA(R) program. At any time, the ROM is mapped at address 0x0040 0000. It is also accessible at address 0x0 (BMS =1) after the reset and before the Remap Command. Boot Strategies The system always boots at address 0x0. To ensure maximum boot possibilities, the memory layout can be changed with two parameters. The AT91CAP9S500A/AT91CAP9S250A Bus Matrix manages a boot memory that depends on the level on the BMS pin at reset. The internal memory area mapped between address 0x0 and 0x000F FFFF is reserved to this effect.
Note: Memory blocks not affected by these parameters can always be seen at their specified base addresses. See the complete memory map presented in Figure 8-1 on page 26.
8.1.1.2
8.1.2
If BMS is detected at 1, the boot memory is the embedded ROM. If BMS is detected at 0, the boot memory is the memory connected on Chip Select 0 of the External Bus Interface. 8.1.2.1 BMS = 1, boot on embedded ROM The system boots on Boot Program. * Boot on on-chip RC oscillator * Auto baudrate detection * Downloads and runs an application from external storage media into internal SRAM * Downloaded code size depends on embedded SRAM size * Automatic detection of valid application
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AT91CAP9S500/AT91CAP9S250A
* Bootloader on a non-volatile memory - NAND Flash - SDCard on MCI0 - SPI DataFlash(R)/Serial Flash connected on NPCS0 and NPCS1 of the SPI0 - EEPROM on TWI * SAM-BA Boot in case no valid program is detected in external NVM, supporting: - Serial communication on a DBGU - USB Device HS Port 8.1.2.2 BMS = 0, boot on external memory * Boot on on-chip RC * Boot with the default configuration for the Static Memory Controller, byte select mode, 16-bit data bus, Read/Write controlled by Chip Select, allows boot on 16-bit non-volatile memory. For optimization purposes, nothing else is done. To speed up the boot sequence user programmed software should perform a complete configuration: * Program the PMC (main oscillator enable or bypass mode) * Program and Start the PLL * Reprogram the SMC setup, cycle, hold, mode timings registers for CS0 to adapt them to the new clock * Switch the main clock to the new value
8.2
External Memories
The external memories are accessed through the External Bus Interfaces. Each Chip Select line has a 256 Mbyte memory area assigned. Refer to Figure 8-1 on page 26.
8.2.1
External Bus Interface The AT91CAP9S500A/AT91CAP9S250A features one External Bus Interface to offer high bandwidth to the system and to prevent any bottleneck while accessing the external memories. * Optimized for Application Memory Space support * Integrates four External Memory Controllers: - Static Memory Controller - 4-port DDR/SDRAM Controller - Burst/Cellular RAM Controller - SLC NAND Flash ECC Controller * Additional logic for NAND Flash and CompactFlashTM * Optional Full 32-bit External Data Bus * Up to 26-bit Address Bus (up to 64 Mbytes linear per chip select) * Up to 6 chip selects, configurable assignment: - Static Memory Controller on NCS0 - Burst/CellularRAM Controller or Static Memory Controller on NCS1 - Static Memory Controller on NCS2
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6264CS-CAP-24-Mar-09
- Static Memory Controller on NCS3, Optional NAND Flash support - Static Memory Controller on NCS4 - NCS5, Optional CompactFlash support * One dedicated chip select: - DDR/SDRAM Controller on SDCS 8.2.2 Static Memory Controller * 8-, 16- or 32-bit Data Bus * Multiple Access Modes supported - Byte Write or Byte Select Lines - Asynchronous read in Page Mode supported (4- up to 32-byte page size) * Multiple device adaptability - Compliant with LCD Module - Control signals programmable setup, pulse and hold time for each Memory Bank * Multiple Wait State Management - Programmable Wait State Generation - External Wait Request - Programmable Data Float Time * Slow Clock mode supported 8.2.3 DDR/SDRAM Controller * Supported devices: - Standard and Low Power SDRAM (Mobile SDRAM) - Mobile DDR * Numerous configurations supported - 2K, 4K, 8K Row Address Memory Parts - SDRAM with two or four Internal Banks - SDRAM with 16- or 32-bit Data Path - Mobile DDR with four Internal Banks - Mobile DDR with 16-bit Data Path * Programming facilities - Word, half-word, byte access - Automatic page break when Memory Boundary has been reached - Multibank Ping-pong Access - Timing parameters specified by software - Automatic refresh operation, refresh rate is programmable - Multiport (4 Ports) * Energy-saving capabilities - Self-refresh, power down and deep power down modes supported * Error detection - Refresh Error Interrupt * DDR/SDRAM Power-up Initialization by software
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* SDRAM CAS Latency of 1, 2 and 3 supported * DDR CAS latency of 3 supported * Auto Precharge Command not used 8.2.4 Burst Cellular RAM Controller * Supported devices: - Synchronous Cellular RAM version 1.0, 1.5 and 2.0 * Numerous configurations supported - 64K, 128K, 256K, 512K Row Address Memory Parts - Cellular RAM with 16- or 32-bit Data Path * Programming facilities - Word, half-word, byte access - Automatic page break when Memory Boundary has been reached - Timing parameters specified by software - Only Continuous read or write burst supported * Energy-saving capabilities - Standby and Deep Power Down (DPD) modes supported - Low Power features (PASR/TCSR) supported * Cellular RAM Power-up Initialization by hardware * Cellular RAM CAS latency of 2 and 3 supported (Version 1.0) * Cellular RAM CAS latency of 2, 3, 4, 5 and 6 supported (Version 1.5 and 2.0) * Cellular RAM variable or fixed latency supported (Version 1.5 and 2.0) * Multiplexed address/data bus supported (Version 2.0) * Asynchronous and Page mode not supported 8.2.5 NAND Flash Error Corrected Code Controller * Hardware Error Corrected Code (ECC) Generation - Detection and Correction by Software * Supports NAND Flash and SmartMediaTM Devices with 8- or 16-bit Data Path * Supports NAND Flash/SmartMedia with Page Sizes of 528, 1056, 2112 and 4224 Bytes Specified by Software * Supports 1 bit correction for a page of 512,1024,2048 and 4096 Bytes with 8- or 16-bit Data Path * Supports 1 bit correction per 512 bytes of data for a page size of 512, 2048 and 4096 Bytes with 8-bit Data Path * Supports 1 bit correction per 256 bytes of data for a page size of 512, 2048 and 4096 Bytes with 8-bit Data Path
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9. System Controller
The System Controller is a set of peripherals, which allow handling of key elements of the system, such as power, resets, clocks, time, interrupts, watchdog, etc. The System Controller User Interface also embeds the registers that allow configuration of the Matrix and a set of registers for the chip configuration. The chip configuration registers are used to configure: - EBI chip select assignment and voltage range for external memories - MP Block The System Controller peripherals are all mapped within the highest 16 Kbytes of address space, between addresses 0xFFFF C000 and 0xFFFF FFFF. However, all the registers of System Controller are mapped on the top of the address space. This allows all the registers of the System Controller to be addressed from a single pointer by using the standard ARM instruction set, as the Load/Store instructions have an indexing mode of 4 Kbytes. Figure 9-1 on page 33 shows the System Controller block diagram. Figure 8-1 on page 26 shows the mapping of the User Interfaces of the System Controller peripherals.
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9.1 System Controller Block Diagram
AT91CAP9S500A/AT91CAP9S250A System Controller Block Diagram
System Controller VDDCORE Powered irq0-irq1 fiq periph_irq[2..29] pit_irq rtt_irq wdt_irq dbgu_irq pmc_irq rstc_irq MCK periph_nreset dbgu_rxd MCK debug periph_nreset SLCK debug idle proc_nreset Periodic Interval Timer Watchdog Timer wdt_fault WDRPROC NRST VDDCORE POR por_ntrst jtag_nreset rstc_irq Reset Controller periph_nreset proc_nreset backup_nreset VDDBU Powered SLCK Real-Time Timer rtt_irq rtt_alarm Debug Unit Advanced Interrupt Controller int por_ntrst ntrst ARM926EJ-S nirq nfiq
Figure 9-1.
dbgu_irq dbgu_txd
proc_nreset PCK debug
pit_irq jtag_nreset wdt_irq MCK periph_nreset Bus Matrix Boundary Scan TAP Controller
VDDBU POR
SLCK backup_nreset
SLCK SHDN WKUP backup_nreset XIN32 XOUT32 SLOW CLOCK OSC rtt_alarm Shut-Down Controller Voltage Controller battery_save
UDPHSCK 4 General-purpose Backup Registers periph_clk[28] periph_nreset USB High-speed Device Port
SLCK UTMI PLL XIN XOUT PLLRCA PLLRCB MAIN OSC PLLA PLLB periph_nreset int UDPHSCK Power Management Controller
periph_clk[2..31] pck[0-3] PCK
periph_irq[28]
MAINCK
UHPCK MCK pmc_irq idle
UHPCK periph_clk[29] periph_nreset periph_irq[29] USB Host Port
PLLACK PLLBCK
periph_clk[7..31] periph_nreset periph_clk[2] dbgu_rxd PA0-PA31 PB0-PB31 PC0-PC31 PD0-PD31 periph_irq[2] irq0-irq1 fiq dbgu_txd periph_nreset periph_irq[7..27] in out enable Embedded Peripherals
PIO Controllers
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9.2
Reset Controller
* Based on two Power-on-Reset cells - One on VDDBU and one on VDDCORE * Status of the last reset - Either general reset (VDDBU rising), wake-up reset (VDDCORE rising), software reset, user reset or watchdog reset * Controls the internal resets and the NRST pin output - Allows shaping a reset signal for the external devices
9.3
Shutdown Controller
* Shutdown and Wake-Up logic - Software programmable assertion of the SHDN pin - Deassertion Programmable on a WKUP pin level change or on alarm
9.4
Clock Generator
* Embeds a low power 32,768 Hz Slow Clock Oscillator and a low power RC oscillator - Provides the permanent Slow Clock SLCK to the system * Embeds the Main Oscillator - Oscillator bypass feature - Supports 8 to 16 MHz crystals - 12 MHz crystal is required for USB High-Speed Device * Embeds 2 programmable PLLs - Output 80 to 240 MHz clocks - Integrates an input divider to increase output accuracy * Embeds 1 UTMI PLL - 480 MHz Fixed frequency from 12 MHz input clock - Integrated filter
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AT91CAP9S500/AT91CAP9S250A
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AT91CAP9S500/AT91CAP9S250A
Figure 9-2. Clock Generator Block Diagram
Clock Generator XIN32 XOUT32 XIN XOUT Main Oscillator Main Clock MAINCK Slow Clock Oscillator Slow Clock SLCK
PLLRCA
PLL and Divider A PLL and Divider B Status Control
PLLA Clock PLLACK PLLB Clock PLLBCK
PLLRCB
Power Management Controller
9.5
Slow Clock Selection
The AT91CAP9S500A/AT91CAP9S250A slow clock can be generated either by an external 32768Hz crystal or the on-chip RC oscillator. The 32768Hz crystal oscillator can be bypassed to accept an external slow clock on XIN32. Configuration is located in the slow clock control register (SCKCR) located at address 0xFFFFFD50 in the backed up part of the system controller and so is preserved while VDDBU is present. Refer to the "Clock Generator" section for more details.
9.6
Power Management Controller
* Provides: - the Processor Clock PCK - the Master Clock MCK, in particular to the Matrix and the memory interfaces - the USB High-speed Device Clock UDPHSCK - the USB Host Clock UHPCK - independent peripheral clocks, typically at the frequency of MCK - four programmable clock outputs: PCK0 to PCK3 * Five flexible operating modes: - Normal Mode, processor and peripherals running at a programmable frequency - Idle Mode, processor stopped waiting for an interrupt - Slow Clock Mode, processor and peripherals running at low frequency - Standby Mode, mix of Idle and Backup Mode, peripheral running at low frequency, processor stopped waiting for an interrupt - Backup Mode, Main Power Supplies off, VDDBU powered by a battery
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6264CS-CAP-24-Mar-09
Figure 9-3.
AT91CAP9S500A/AT91CAP9S250A Power Management Controller Block Diagram
Processor Clock Controller Master Clock Controller SLCK MAINCK PLLACK PLLBCK Prescaler /1,/2,/4,...,/64 Divider /1,/2,/4 Peripherals Clock Controller ON/OFF DDRCK Programmable Clock Controller SLCK MAINCK PLLACK PLLBCK ON/OFF Prescaler /1,/2,/4,...,/64 pck[..] Idle Mode MCK
PCK int
periph_clk[..]
USB Clock Controller PLLBCK Divider /1,/2,/4 ON/OFF UHPCK
9.7
Periodic Interval Timer
* Includes a 20-bit Periodic Counter, with less than 1 s accuracy * Includes a 12-bit Interval Overlay Counter * Real-time OS or Linux(R)/WinCE(R) compliant tick generator
9.8
Watchdog Timer
* 16-bit key-protected only-once-Programmable Counter * Windowed, prevents the processor to be in a dead-lock on the watchdog access
9.9
Real-time Timer
* Two Real-time Timers, allowing backup of time with different accuracies - 32-bit Free-running back-up Counter - Integrates a 16-bit programmable prescaler running on the embedded 32,768 Hz oscillator - Alarm Register to generate a wake-up of the system through the Shutdown Controller
9.10
General-Purpose Backup Registers
* Four 32-bit backup general-purpose registers
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9.11 Advanced Interrupt Controller
* Controls the interrupt lines (nIRQ and nFIQ) of the ARM Processor * Thirty-two individually maskable and vectored interrupt sources - Source 0 is reserved for the Fast Interrupt Input (FIQ) - Source 1 is reserved for system peripherals (PIT, RTT, PMC, DBGU, etc.) - Programmable Edge-triggered or Level-sensitive Internal Sources - Programmable Positive/Negative Edge-triggered or High/Low Level-sensitive * Four External Sources plus the Fast Interrupt signal * 8-level Priority Controller - Drives the Normal Interrupt of the processor - Handles priority of the interrupt sources 1 to 31 - Higher priority interrupts can be served during service of lower priority interrupt * Vectoring - Optimizes Interrupt Service Routine Branch and Execution - One 32-bit Vector Register per interrupt source - Interrupt Vector Register reads the corresponding current Interrupt Vector * Protect Mode - Easy debugging by preventing automatic operations when protect models are enabled * Fast Forcing - Permits redirecting any normal interrupt source on the Fast Interrupt of the processor
9.12
Debug Unit
* Composed of two functions - Two-pin UART - Debug Communication Channel (DCC) support * Two-pin UART - Implemented features are 100% compatible with the standard Atmel USART - Independent receiver and transmitter with a common programmable Baud Rate Generator - Even, Odd, Mark or Space Parity Generation - Parity, Framing and Overrun Error Detection - Automatic Echo, Local Loopback and Remote Loopback Channel Modes - Support for two PDC channels with connection to receiver and transmitter * Debug Communication Channel Support - Offers visibility of and interrupt trigger from COMMRX and COMMTX signals from the ARM Processor's ICE Interface
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6264CS-CAP-24-Mar-09
9.13
Chip Identification
* Chip ID: 0x039A03A1 (for DevChip) * JTAG ID: 0x15B1B03F * ARM926 TAP ID: 0x0792603F
9.14
PIO Controllers
* 4 PIO Controllers, PIOA to PIOD, controlling a total of 128 I/O Lines * Each PIO Controller controls up to 32 programmable I/O Lines - PIOA has 32 I/O Lines - PIOB has 32 I/O Lines - PIOC has 32 I/O Lines - PIOD has 32 I/O Lines * Fully programmable through Set/Clear Registers * Multiplexing of two peripheral functions per I/O Line * For each I/O Line (whether assigned to a peripheral or used as general purpose I/O) - Input change interrupt - Glitch filter - Multi-drive option enables driving in open drain - Programmable pull up on each I/O line - Pin data status register, supplies visibility of the level on the pin at any time * Synchronous output, provides Set and Clear of several I/O lines in a single write
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AT91CAP9S500/AT91CAP9S250A
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AT91CAP9S500/AT91CAP9S250A
10. Peripherals
10.1 User Interface
The peripherals are mapped in the upper 256 Mbytes of the address space between the addresses 0xFFFA 0000 and 0xFFFC FFFF. Each user peripheral is allocated 16 Kbytes of address space. A complete memory map is presented in Figure 8-1 on page 26.
10.2
Identifiers
The AT91CAP9S500A/AT91CAP9S250A embeds a wide range of peripherals. Table 10-1 defines the Peripheral Identifiers of the AT91CAP9S500A/AT91CAP9S250A. A peripheral identifier is required for the control of the peripheral interrupt with the Advanced Interrupt Controller and for the control of the peripheral clock with the Power Management Controller. Table 10-1.
Peripheral ID 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
AT91CAP9S500A/AT91CAP9S250A Peripheral Identifiers
Peripheral Mnemonic AIC SYSC PIOA-D MPB0 MPB1 MPB2 MPB3 MPB4 US0 US1 US2 MCI0 MCI1 CAN TWI SPI0 SPI1 SSC0 SSC1 AC97 TC0, TC1, TC2 PWMC EMAC Reserved Peripheral Name Advanced Interrupt Controller System Controller Interrupt Parallel I/O Controller A to D MP Block Peripheral 0 MP Block Peripheral 1 MP Block Peripheral 2 MP Block Peripheral 3 MP Block Peripheral 4 USART 0 USART 1 USART 2 Multimedia Card Interface 0 Multimedia Card Interface 1 CAN Controller Two-Wire Interface Serial Peripheral Interface 0 Serial Peripheral Interface 1 Synchronous Serial Controller 0 Synchronous Serial Controller 1 AC97 Controller Timer/Counter 0, 1 and 2 Pulse Width Modulation Controller Ethernet MAC Reserved External Interrupt FIQ
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6264CS-CAP-24-Mar-09
Table 10-1.
Peripheral ID 24 25 26 27 28 29 30 31
AT91CAP9S500A/AT91CAP9S250A Peripheral Identifiers (Continued)
Peripheral Mnemonic ADCC ISI LCDC DMA UDPHS UHP AIC AIC Peripheral Name ADC Controller Image Sensor Interface LCD Controller DMA Controller USB High Speed Device Port USB Host Port Advanced Interrupt Controller Advanced Interrupt Controller IRQ0 IRQ1 External Interrupt
10.2.1 10.2.1.1
Peripheral Interrupts and Clock Control System Interrupt The System Interrupt in Source 1 is the wired-OR of the interrupt signals coming from: * the DDR/SDRAM Controller * the BCRAM Controller * the Debug Unit * the Periodic Interval Timer * the Real-Time Timer * the Watchdog Timer * the Reset Controller * the Power Management Controller * the MP Block The clock of these peripherals cannot be deactivated and Peripheral ID 1 can only be used within the Advanced Interrupt Controller.
10.2.1.2
External Interrupts All external interrupt signals, i.e., the Fast Interrupt signal FIQ or the Interrupt signals IRQ0 to IRQ1, use a dedicated Peripheral ID. However, there is no clock control associated with these peripheral IDs. Timer Counter Interrupts The three Timer Counter channels interrupt signals are OR-wired together to provide the interrupt source 19 of the Advanced Interrupt Controller. This forces the programmer to read all Timer Counter status registers before branching the right Interrupt Service Routine. The Timer Counter channels clocks cannot be deactivated independently. Switching off the clock of the Peripheral 19 disables the clock of the 3 channels.
10.2.1.3
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AT91CAP9S500/AT91CAP9S250A
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AT91CAP9S500/AT91CAP9S250A
10.2.2 DMA Controller Request Signals The requests to the DMA Controller may come from eight different sources: * four external requests * four internal requests from the MPBlock
Table 10-2.
DMA Controller Request Source and Signal Names
Internal DMA Request from MPBlock External DMA Request Channel 3 DMARQ3 Channel 2 DMARQ2 Channel 1 DMARQ1 Channel 0 DMARQ0
Channel 7 MP_DMARQ3
Channel 6 MP_DMARQ2
Channel 5 MP_DMARQ1
Channel 4 MP_DMARQ0
Each request source is selected through the DMAC Channel x Configuration Register. It is also necessary to choose the hardware handshaking interface from the SRC_H2SEL and DST_H2SEL fields. (For more details, see the DMA Controller (DMAC) section and DMAC User Interface in the product datasheet.)
10.3
Peripheral Signal Multiplexing on I/O Lines
The AT91CAP9S500A/AT91CAP9S250A features 4 PIO controllers, PIOA, PIOB, PIOC and PIOD, that multiplex the I/O lines of the peripheral set. Each PIO Controller controls up to 32 lines. Each line can be assigned to one of two peripheral functions, A or B. The multiplexing tables in the following paragraphs define how the I/O lines of the peripherals A and B are multiplexed on the PIO Controllers. The two columns "Function" and "Comments" have been inserted in this table for the user's own comments; they may be used to track how pins are defined in an application. Note that some peripheral functions which are output only may be duplicated within both tables. The column "Reset State" indicates whether the PIO Line resets in I/O mode or in peripheral mode. If I/O is mentioned, the PIO Line resets in input with the pull-up enabled, so that the device is maintained in a static state as soon as the reset is released. As a result, the bit corresponding to the PIO Line in the register PIO_PSR (Peripheral Status Register) resets low. If a signal name is mentioned in the "Reset State" column, the PIO Line is assigned to this function and the corresponding bit in PIO_PSR resets high. This is the case of pins controlling memories, in particular the address lines, which require the pin to be driven as soon as the reset is released. Note that the pull-up resistor is also enabled in this case.
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6264CS-CAP-24-Mar-09
10.3.1
PIO Controller A Multiplexing Multiplexing on PIO Controller A
PIO Controller A Application Usage Comments Reset State I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O PWM1 PWM3 PCK0 I/O I/O I/O I/O IRQ1 PCK2 ISI_D0 ISI_D1 ISI_D2 ISI_D3 ISI_D4 ISI_D5 ISI_D6 ISI_D7 ISI_PCK ISI_HSYNC ISI_VSYNC ISI_MCK ISI_D8 ISI_D9 ISI_D10 ISI_D11 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Power Supply VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 can be removed can be removed can be removed can be removed can be removed can be removed can be removed can be removed can be removed can be removed can be removed can be removed can be removed can be removed can be removed can be removed Function 324-BGA pkg Options(1)
Table 10-3.
I/O Line PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PA8 PA9 PA10 PA11 PA12 PA13 PA14 PA15 PA16 PA17 PA18 PA19 PA20 PA21 PA22 PA23 PA24 PA25 PA26 PA27 PA28 PA29 PA30 PA31 Note:
Peripheral A MCI0_D0 MCI0_CD MCI0_CK MCI0_D1 MCI0_D2 MCI0_D3 AC97FS AC97CK AC97TX AC97RX IRQ0 DMARQ0 CANTX CANRX TCLK2 DMARQ3 MCI1_CK MCI1_CD MCI1_D0 MCI1_D1 MCI1_D2 MCI1_D3 TXD0 RXD0 RTS0 CTS0 SCK0 PCK1 SPI0_NPCS3 TIOA0 TIOB0 DMARQ1
Peripheral B SPI0_MISO SPI0_MOSI SPI0_SPCK SPI0_NPCS1 SPI0_NPCS2 SPI0_NPCS0
1. The user must ensure that removing the designated pins does not have an adverse effect on the intended application.
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10.3.2 PIO Controller B Multiplexing Multiplexing on PIO Controller B
PIO Controller B I/O Line PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PB8 PB9 PB10 PB11 PB12 PB13 PB14 PB15 PB16 PB17 PB18 PB19 PB20 PB21 PB22 PB23 PB24 PB25 PB26 PB27 PB28 PB29 PB30 PB31 Note: Peripheral A TF0 TK0 TD0 RD0 RK0 RF0 TF1 TK1 TD1 RD1 RK1 RF1 SPI1_MISO SPI1_MOSI SPI1_SPCK SPI1_NPCS0 SPI1_NPCS1 SPI1_NPCS2 SPI1_NPCS3 PWM0 PWM1 ETXCK/EREFCK ERXDV ETX0 ETX1 ERX0 ERX1 ERXER ETXEN EMDC EMDIO ADTRIG EF100 TCLK0 PWM3 TIOA2 TIOB2 PCK3 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 TWD TWCK TIOA1 TIOB1 PWM2 LCDCC PCK1 Peripheral B Comments Reset State I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Application Usage Power Supply VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 can be removed can be removed can be removed can be removed can be removed can be removed can be removed can be removed can be removed can be removed can be removed Function 324-BGA pkg Options(1)
Table 10-4.
1. The user must ensure that removing the designated pins does not have an adverse effect on the intended application.
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6264CS-CAP-24-Mar-09
10.3.3
PIO Controller C Multiplexing Multiplexing on PIO Controller C
PIO Controller C Application Usage Comments Reset State I/O I/O I/O PWM1 LCDD3 LCDD4 LCDD5 LCDD6 LCDD7 LCDD10 LCDD11 LCDD12 LCDD13 LCDD14 LCDD15 LCDD19 LCDD20 LCDD21 LCDD22 LCDD23 ETX2 ETX3 ERX2 ERX3 ETXER ECRS ECOL ERXCK TCLK1 PWM2 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Power Supply VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 Function 324-BGA pkg Options(1) can be removed can be removed can be removed can be removed can be removed can be removed can be removed can be removed can be removed can be removed can be removed can be removed can be removed can be removed can be removed can be removed can be removed can be removed can be removed can be removed can be removed can be removed can be removed can be removed can be removed can be removed can be removed can be removed
Table 10-5.
I/O Line PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PC8 PC9 PC10 PC11 PC12 PC13 PC14 PC15 PC16 PC17 PC18 PC19 PC20 PC21 PC22 PC23 PC24 PC25 PC26 PC27 PC28 PC29 PC30 PC31 Note:
Peripheral A LCDVSYNC LCDHSYNC LCDDOTCK LCDDEN LCDD0 LCDD1 LCDD2 LCDD3 LCDD4 LCDD5 LCDD6 LCDD7 LCDD8 LCDD9 LCDD10 LCDD11 LCDD12 LCDD13 LCDD14 LCDD15 LCDD16 LCDD17 LCDD18 LCDD19 LCDD20 LCDD21 LCDD22 LCDD23 PWM0 PCK0 DRXD DTXD
Peripheral B
1. The user must ensure that removing the designated pins does not have an adverse effect on the intended application.
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10.3.4 PIO Controller D Multiplexing Multiplexing on PIO Controller D
PIO Controller D I/O Line PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD8 PD9 PD10 PD11 PD12 PD13 PD14 PD15 PD16 PD17 PD18 PD19 PD20 PD21 PD22 PD23 PD24 PD25 PD26 PD27 PD28 PD29 PD30 PD31 Note: Peripheral A TXD1 RXD1 TXD2 RXD2 FIQ DMARQ2 NWAIT NCS4/CFCS0 NCS5/CFCS1 CFCE1 CFCE2 NCS2 A23 A24 A25/CFRNW NCS3/NANDCS D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 RTS2 CTS2 RTS1 CTS1 SCK2 SCK1 Peripheral B SPI0_NPCS2 SPI0_NPCS3 SPI1_NPCS2 SPI1_NPCS3 Comments Reset State I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O A23 A24 A25 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Application Usage Power Supply VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM Function 324-BGA pkg Options(1) can be removed can be removed can be removed can be removed can be removed can be removed can be removed can be removed can be removed can be removed can be removed
Table 10-6.
1. The user must ensure that removing the designated pins does not have an adverse effect on the intended application.
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6264CS-CAP-24-Mar-09
10.4
10.4.1
Embedded Peripherals
Serial Peripheral Interface * Supports communication with serial external devices - Four chip selects with external decoder support allow communication with up to 15 peripherals - Serial memories, such as DataFlash and 3-wire EEPROMs - Serial peripherals, such as ADCs, DACs, LCD Controllers, CAN Controllers and Sensors - External co-processors * Master or slave serial peripheral bus interface - 8- to 16-bit programmable data length per chip select - Programmable phase and polarity per chip select - Programmable transfer delays between consecutive transfers and between clock and data per chip select - Programmable delay between consecutive transfers - Selectable mode fault detection * Very fast transfers supported - Transfers with baud rates up to MCK - The chip select line may be left active to speed up transfers on the same device
10.4.2
Two-wire Interface * Compatibility with standard two-wire serial memory * One, two or three bytes for slave address * Sequential read/write operations
10.4.3
USART * Programmable Baud Rate Generator * 5- to 9-bit full-duplex synchronous or asynchronous serial communications - 1, 1.5 or 2 stop bits in Asynchronous Mode or 1 or 2 stop bits in Synchronous Mode - Parity generation and error detection - Framing error detection, overrun error detection - MSB- or LSB-first - Optional break generation and detection - By 8 or by-16 over-sampling receiver frequency - Hardware handshaking RTS-CTS - Receiver time-out and transmitter timeguard - Optional Multi-drop Mode with address generation and detection - Optional Manchester Encoding * RS485 with driver control signal * ISO7816, T = 0 or T = 1 Protocols for interfacing with smart cards - NACK handling, error counter with repetition and iteration limit
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AT91CAP9S500/AT91CAP9S250A
6264CS-CAP-24-Mar-09
AT91CAP9S500/AT91CAP9S250A
* IrDA modulation and demodulation - Communication at up to 115.2 Kbps * Test Modes - Remote Loopback, Local Loopback, Automatic Echo 10.4.4 Synchronous Serial Controller * Provides serial synchronous communication links used in audio and telecom applications (with CODECs in Master or Slave Modes, I2S, TDM Buses, Magnetic Card Reader, etc.) * Contains an independent receiver and transmitter and a common clock divider * Offers a configurable frame sync and data length * Receiver and transmitter can be programmed to start automatically or on detection of different event on the frame sync signal * Receiver and transmitter include a data signal, a clock signal and a frame synchronization signal 10.4.5 AC97 Controller * Compatible with AC97 Component Specification V2.2 * Capable to Interface with a Single Analog Front end * Three independent RX Channels and three independent TX Channels - One RX and one TX channel dedicated to the AC97 Analog Front end control - One RX and one TX channel for data transfers, associated with a PDC - One RX and one TX channel for data transfers with no PDC * Time Slot Assigner allowing to assign up to 12 time slots to a channel * Channels support mono or stereo up to 20 bit sample length - Variable sampling rate AC97 Codec Interface (48KHz and below) 10.4.6 Timer Counter * Three 16-bit Timer Counter Channels * Wide range of functions including: - Frequency Measurement - Event Counting - Interval Measurement - Pulse Generation - Delay Timing - Pulse Width Modulation - Up/down Capabilities * Each channel is user-configurable and contains: - Three external clock inputs - Five internal clock inputs - Two multi-purpose input/output signals * Two global registers that act on all three TC Channels
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6264CS-CAP-24-Mar-09
10.4.7
Pulse Width Modulation Controller * 4 channels, one 16-bit counter per channel * Common clock generator, providing Thirteen Different Clocks - A Modulo n counter providing eleven clocks - Two independent Linear Dividers working on modulo n counter outputs * Independent channel programming - Independent Enable Disable Commands - Independent Clock Selection - Independent Period and Duty Cycle, with Double Buffering - Programmable selection of the output waveform polarity - Programmable center or left aligned output waveform
10.4.8
Multimedia Card Interface * 2 double-channel Multimedia Card Interface, allowing concurrent transfers with 2 cards * Compatibility with MultiMedia Card Specification Version 3.31 * Compatibility with SD Memory Card Specification Version 1.0 * Compatibility with SDIO Specification Version V1.0. * Cards clock rate up to Master Clock divided by 2 * Embedded power management to slow down clock rate when not used * Each MCI has one slot supporting - One MultiMediaCard bus (up to 30 cards) or - One SD Memory Card - One SDIO Card * Support for stream, block and multi-block data read and write
10.4.9
CAN Controller * Fully compliant with 16-mailbox CAN 2.0A and 2.0B CAN Controllers * Bit rates up to 1Mbit/s. * Object-oriented mailboxes, each with the following properties: - CAN Specification 2.0 Part A or 2.0 Part B Programmable for Each Message - Object Configurable as receive (with overwrite or not) or transmit - Local Tag and Mask Filters up to 29-bit Identifier/Channel - 32 bits access to Data registers for each mailbox data object - Uses a 16-bit time stamp on receive and transmit message - Hardware concatenation of ID unmasked bitfields to speedup family ID processing - 16-bit internal timer for Time Stamping and Network synchronization - Programmable reception buffer length up to 16 mailbox object - Priority Management between transmission mailboxes - Autobaud and listening mode - Low power mode and programmable wake-up on bus activity or by the application - Data, Remote, Error and Overload Frame handling
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AT91CAP9S500/AT91CAP9S250A
6264CS-CAP-24-Mar-09
AT91CAP9S500/AT91CAP9S250A
10.4.10 USB Host Port * Compliance with OHCI Rev 1.0 Specification * Compliance with USB V2.0 Full-speed and Low-speed Specification * Supports both Low-speed 1.5 Mbps and Full-speed 12 Mbps devices * Root hub integrated with two downstream USB ports * Two embedded USB transceivers * Supports power management * Operates as a master on the Matrix * Internal DMA Controller, operating as a Master on Bus Matrix 10.4.11 USB High Speed Device Port * USB V2.0 high-speed compliant, 480 MBits per second * Embedded USB V2.0 UTMI+ high-speed transceiver * Embedded 4K-byte dual-port RAM for endpoints * Embedded 6 channels DMA controller * Suspend/Resume logic * Up to 2 or 3 banks for isochronous and bulk endpoints * Seven endpoints: - Endpoint 0: 64 bytes - Endpoint 1 & 2: 1024 bytes, 3 banks mode, HS isochronous capable - Endpoint 3 & 4: 1024 bytes, 2 banks mode, HS isochronous capable - Endpoint 5 & 6: 1024 bytes, 2 banks mode - Endpoint 7: 1024 bytes, 2 banks mode 10.4.12 LCD Controller * Single and Dual scan color and monochrome passive STN LCD panels supported * Single scan active TFT LCD panels supported * 4-bit single scan, 8-bit single or dual scan, 16-bit dual scan STN interfaces supported * Up to 24-bit single scan TFT interfaces supported * Up to 16 gray levels for mono STN and up to 4096 colors for color STN displays * 1, 2 bits per pixel (palletized), 4 bits per pixel (non-palletized) for mono STN * 1, 2, 4, 8 bits per pixel (palletized), 16 bits per pixel (non-palletized) for color STN * 1, 2, 4, 8 bits per pixel (palletized), 16, 24 bits per pixel (non-palletized) for TFT * Single clock domain architecture * Resolution supported up to 2048x2048 * 2D-DMA Controller for management of virtual Frame Buffer - Allows management of frame buffer larger than the screen size and moving the view over this virtual frame buffer * Automatic resynchronization of the frame buffer pointer to prevent flickering
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6264CS-CAP-24-Mar-09
10.4.13
Ethernet 10/100 MAC * Compatibility with IEEE Standard 802.3 * 10 and 100 MBits per second data throughput capability * Full- and half-duplex operations * MII or RMII interface to the physical layer * Register Interface to address, data, status and control registers * Internal DMA Controller, operating as a Master on Bus Matrix * Interrupt generation to signal receive and transmit completion * 28-byte transmit and 28-byte receive FIFOs * Automatic pad and CRC generation on transmitted frames * Address checking logic to recognize four 48-bit addresses * Support promiscuous mode where all valid frames are copied to memory * Support physical layer management through MDIO interface control of alarm and update time/calendar data in
10.4.14
Image Sensor Interface * ITU-R BT. 601/656 8-bit mode external interface support * Support for ITU-R BT.656-4 SAV and EAV synchronization * Vertical and horizontal resolutions up to 2048 x 2048 * Preview Path up to 640*480 * Support for packed data formatting for YCbCr 4:2:2 formats * Preview scaler to generate smaller size image * Programmable frame capture rate * Internal DMA Controller, operating as a Master on Bus Matrix
10.4.15
Analog-to-digital Converter * 8-channel ADC * 10-bit 440K samples/sec. Successive Approximation Register ADC * -2/+2 LSB Integral Non Linearity, -1/+1 LSB Differential Non Linearity * Individual enable and disable of each channel * External voltage reference for better accuracy on low voltage inputs * Multiple trigger source - Hardware or software trigger - External trigger pin - Timer Counter 0 to 2 outputs TIOA0 to TIOA2 and TIOB0 to TIOB2 triggers * Sleep Mode and conversion sequencer - Automatic wakeup on trigger and back to sleep mode after conversions of all enabled channels * Four analog inputs shared with digital signals
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AT91CAP9S500/AT91CAP9S250A
6264CS-CAP-24-Mar-09
AT91CAP9S500/AT91CAP9S250A
11. Metal Programmable Block
The Metal Programmable Block (MPBlock) is connected to internal resources as the AHB bus or interrupts and to external resources as dedicated I/O pads or UTMI+ core. The MPBlock may be used to implement the Advanced High-speed Bus (AHB) or Advanced Peripheral Bus (APB) custom peripherals. The MPBlock adds approximately 500K or 250K gates of standard cell custom logic to the AT91CAP9S500A/AT91CAP9S250A base design. Figure 11-1 shows the MPBlock and its connections to internal or external resources. Figure 11-1. MPBlock Connectivity
ITs DMA AHB MASTERS AHB SLAVES
MPBlock Test Wrapper 10x CLOCKS CAN, MACB, OHCI ENABLE MPBLOCK 500K Gates (CAP9500) 250K Gates (CAP9250) DPR 512x36
8x SPR 512x72
CHIP ID JTAG ID
UTMI+ PHY
Chip Boundary Scan
MPIOA[31:0]
MPIOB[44:0]
11.1
Internal Connectivity
In order to connect the MPBlock custom peripheral to the AT91CAP9S500A/AT91CAP9S250A base design, the following connections are made.
11.1.1
Clocks The MPBlock receives the following clocks: * 32,768 Hz Slow Clock * 8 to 16 MHz Main Oscillator Clock * PLLA Clock * PLLB Clock * 48 MHz USB Clock * 12 MHz USB Clock
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6264CS-CAP-24-Mar-09
* 30 or 60 MHz UTMI+ USB Clock * MCK System Clock * DDRCK Dual Rate System Clock * PCK Processor Clock * 5 Gated Peripheral Clocks (for AHB and/or APB peripherals) corresponding to Peripheral ID 3 to 7 11.1.2 AHB Master Buses The MPBlock may implement up to three AHB masters, each having a dedicated AHB master bus connected to the Bus Matrix. AHB Slave Buses The MPBlock receives four different AHB slave buses coming from the Bus Matrix. Each bus has two or four select signals that can implement up to 12 AHB slaves. Interrupts The MPBlock is connected to 5 dedicated interrupt lines corresponding to Peripheral ID 3 to 9. It is also connected to two other interrupt lines (through OR gate) corresponding to Peripheral ID 1 and 2 11.1.5 DMA Channels The MPBlock is connected to 4 DMA hardware handshaking interfaces, allowing it to implement up to 4 DMA enabled peripherals. Peripheral DMA Channels The MPBlock is not connected to the Peripheral DMA Controller. In order to implement Peripheral DMA Controller (PDC) enabled APB peripherals, a PDC and an AHB-to-APB Bridge must be integrated into the MPBlock using one AHB master and one AHB slave bus. MPBlock Single Port RAMs The MPBlock is connected to eight instances of 512x72 High-Speed Single Port RAMs. The MPBlock has control over all memory connections. 11.1.8 MPBlock Dual Port RAMs The MPBlock is connected to ten instances of 512x36 High-Speed Dual Port RAMs. The MPBlock has control over all memory connections. 11.1.9 Optional Peripherals Enable The MPBlock drives the enable of the optional peripherals, and so can enable or disable any of the optional peripherals.
11.1.3
11.1.4
11.1.6
11.1.7
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AT91CAP9S500/AT91CAP9S250A
6264CS-CAP-24-Mar-09
AT91CAP9S500/AT91CAP9S250A
11.2 External Connectivity
The MPBlock is connected to the following external resources. 11.2.1 Dedicated I/O Lines The MPBlock is directly connected to 77 (32 MPIOA and 45 MPIOB lines) dedicated I/O Pads with the following features: * Supply/Drive control pin (needed for high-speed or low voltage interfaces) * Pull-up control pin * Supported logic levels include: - LVCMOS33 at 100 MHz maximum frequency - LVCMOS25 at 50 MHz maximum frequency - LVCMOS18 at 100 MHz maximum frequency 11.2.2 UTMI+ Transceiver The MPBlock may be connected to the UTMI+ transceiver. As only one UTMI+ transceiver is available, the USB High-speed Device and the MPBlock do not have access to the UTMI+ at the same time. However, a dual role Master-Slave USB High-Speed may be implemented by using the USB High-speed Device and integrating a High-speed Host in the MPBlock as the switching between both is generated inside the MPBlock.
11.3
Prototyping Solution
In order to prototype the final custom design, a Prototyping Platform version of the AT91CAP9S500A/AT91CAP9S250A design has been created. The platform maps APB and AHB masters or slaves into the FPGA located outside the chip with the following features and restrictions: * AT91CAP9S500A/AT91CAP9S250A to FPGA interface is provided to prototype AHB masters and slave into the external FPGA exactly as if it were in MPBlock. * Prototyped AHB Masters - Prototyped AHB Masters have access to AT91CAP9S500A/AT91CAP9S250A slave resources. - Prototyped AHB Masters have access to MPBlock (FPGA) slave resources. * Prototyped AHB Slaves - Prototyped AHB Slaves may be accessed from AT91CAP9S500A/AT91CAP9S250A master resources. - Prototyped AHB Slaves may be accessed from MPBlock (FPGA) resources. * Prototyped APB Slaves - APB bus must be created locally in the FPGA by implementing AHB to APB bridge. Peripheral DMA controller may also be necessary to implement locally in the FPGA in order to prototype PDC enabled APB peripherals. Figure 11-2 shows a typical prototyping solution.
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6264CS-CAP-24-Mar-09
Figure 11-2. Typical Prototyping Solution
CAP9500 CAP9250
MASTERS
ARM926EJ-S
EBI Bus Matrix
4-channel DMA
Metal Programmable Block 500K Gates (CAP9500) 250K Gates (CAP9250) FPGA Interface
MPIOA[31:0]
MPIOB[44:0] FPGA
CAP9500/CAP9250 FPGA Interface Local AHB Matrix
AHB MASTER
DPR
AHB 2 APB BRIDGE
PDC
RAM
AHB MASTER
AHB SLAVE
DPR
APB DPR
APB SLAVE APB SLAVE
MPBlock Emulation Area
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AT91CAP9S500/AT91CAP9S250A
6264CS-CAP-24-Mar-09
AT91CAP9S500/AT91CAP9S250A
12. AT91CAP9S Mechanical Characteristics
12.1 Package Drawing
Figure 12-1. 400-ball LFBGA Package Drawing
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6264CS-CAP-24-Mar-09
Figure 12-2. 324-ball TFBGA Package
56
AT91CAP9S500/AT91CAP9S250A
6264CS-CAP-24-Mar-09
AT91CAP9S500/AT91CAP9S250A
13. AT91CAP9S Ordering Information
Table 13-1. CAP9S Ordering Information
Package BGA400 AT91CAP9S500A-CJ AT91CAP9S250A-CJ BGA324 AT91CAP9S500A-CJ RoHS Compliant Package Type RoHS Compliant Temperature Operating Range Industrial -40C to 85C Industrial -40C to 85C
Ordering Code AT91CAP9S250A-CJ
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6264CS-CAP-24-Mar-09
14. Revision History
Change Request Ref. 5553/5242
Document Ref. 6264CS
Comments Datasheet update corresponds to the most recent version of the CAP9S and includes the following:. Added new sections: Section 8.1.1.2 "Internal ROM" Section 8.1.2 "Boot Strategies" Section 8.2.5 "NAND Flash Error Corrected Code Controller" Section 9.5 "Slow Clock Selection" includes Updates to: "Features" , - 32 Kbyte Internal ROM - 128-byte FIFOs - Selectable 32768 Hz Low-power Oscillator or Internal Low-power RC Oscillator *Two MultiMedia Card Interfaces Section 4.4 "324-ball TFBGA Package Pinout", text updated with PD0-PD10. Table 3-1, "Signal Description List" under "DDR/SDRAM Controller"
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DQM0 - DQM1 signals for "DDR Data Masks", added to table.
Table 4-1, "AT91CAP9S500A/AT91CAP9S250A Pinout for 400-ball BGA Package" T5 pin = "SDCS" . Section 6.3 "Reset Pins", updated. Section 8. "Memories", 2nd paragraph updated EBI/external chip selects. Section 8.1 "Embedded Memories", 32 Kbyte ROM - double cycle access..... Section 8.2.1 "External Bus Interface", updated. Section 9.4 "Clock Generator", updated. Section 9.13 "Chip Identification", updated. Figure 2-1, Block Diagram updated with SDCS signal Previously named chapters; Boot Memory and Boot Program replaced by: Section 8.1.1.2 "Internal ROM", Section 8.1.2 "Boot Strategies", Section 8.1.2.1 "BMS = 1, boot on embedded ROM", Section 8.1.2.2 "BMS = 0, boot on external memory", Table 8-1, "Internal Memory Mapping", Updated Update: Section 8.2.1 "External Bus Interface", Integrates four External Memory Controllers. Reference to SLC NAND Flash ECC Controller updated. Section 8.2.5 "NAND Flash Error Corrected Code Controller", replaces Error Corrected Code Controller
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AT91CAP9S500/AT91CAP9S250A
6264CS-CAP-24-Mar-09
AT91CAP9S500/AT91CAP9S250A
Document Ref. Change Request Ref.
Comments "Features" PIOD typo fixed. "Required Power Supplies:" on page 3, important update and new supplies added. "One 8-channel, 10-bit Analog-to-Digital Converter (ADC)" , added to features Section 10.4.15 "Analog-to-digital Converter", added. "Features" 32-ball BGA Package added. Section 4. "Package and Pinout", 324-ball TFBGA package added. Figure 4-2, "324-ball TFBGA Package Outline and Marking (Top View)," on page 15, added. Figure 12-2, "324-ball TFBGA Package," on page 56, added. Figure 2-1 on page 4, Block Diagram updated Table 3-1, "Signal Description List" 324-ball TFBGA package options added in note to MPBLOCK parameters. Section 10.3.1 on page 42, Section 10.3.2 on page 43, Section 10.3.3 on page 44, Section 10.3.4 on page 45, Multiplexing on PIO I/Os updated with 324-ball TFBGA options. Section 10.4.11 "USB High Speed Device Port", Endpoint information corrected. Figure 8-1, "AT91CAP9S500A/AT91CAP9S250A Memory Mapping," on page 26, note associated with "boot memory" updated. Table 8-1, "Internal Memory Mapping," on page 28, updated. Figure 4-1, "400-ball LFBGA Package Outline and Marking (Top View)," on page 11, updated with package marking. Section 10.2.2 "DMA Controller Request Signals", section added. Section 10.4.11 "USB High Speed Device Port", endpoints 3 and 4 are "HS isochronous capable".
6246BS
4490
4916
4263
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6264AS
First issue.
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6264CS-CAP-24-Mar-09
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6264CS-CAP-24-Mar-09

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